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hyb18t512161cf?[16/20] 512-mbit x16 ddr2 sdram ddr2 sdram eu rohs compliant internet data sheet rev. 1.11 august 2008
internet data sheet hyb18t512161cf 512-mbit double-data-rate-two sdram qag_techdoc_a4, 4.20, 2008-01-25 2 07222008-fvt6-k01b we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com hyb18t512161cf?[16/20] revision history: 2008-08, rev. 1.11 page subjects (major chang es since last revision) all removed 400 mhz previous revision:1.10, 2007-07 all adapted internet edition
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 3 07222008-fvt6-k01b 1overview this chapter gives an overview of the 512-mbit double-d ata-rate-two sdram product family for graphics applications and describes its main characteristics. 1.1 features the 512-mbit double-data-rate-two sdra m offers the following key features: ?1.8v 0.1 v v dd for [?16/?20] ?1.8v 0.1 v v ddq for [?16/?20] ? dram organizations with 16 data in/outputs ? double data rate architecture: ? two data transfers per clock cycle ? four internal banks for concurrent operation ? programmable cas latency: 3, 4, 5, 6, 7 ? programmable burst length: 4 and 8 ? differential clock inputs (ck and ck ) ? bi-directional, differentia l data strobes (dqs and dqs ) are transmitted / received with da ta. edge aligned with read data and center-aligned with write data. ? dll aligns dq and dqs transitions with clock ?dqs can be disabled for single-ended data strobe operation ? commands entered on each positive clock edge, data and data mask are referenced to both edges of dqs ? data masks (dm) for write data ? posted cas by programmable additive latency (0-6) for better command and data bus efficiency ? off-chip-driver impedance adjustment (ocd) and on- die-termination (odt) for better signal quality. ? auto-precharge operation for read and write bursts ? auto-refresh, self-refresh and power saving power- down modes ? average refresh period 7.8 s at a t case lower than 85c, 3.9 s between 85c and 95c ? full strength and reduced strength (60%) data-output drivers ? 2 k page size ? package: p-tfbga-84 ? rohs compliant products 1) table 1 ordering information for rohs compliant products 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product number org. clock (mhz) package hyb18t512161cf?[16/20] 16 600/500 p-tfbga-84
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 4 07222008-fvt6-k01b 1.2 description the 512-mbit ddr2 sdram is a high-speed double-data-rate -two cmos synchronous dram device containing 536, 870, 912 bits and internally configured as a quad bank dram. the 512-mb device is organized as 8 mbit 16 i/o 4 banks chip. these synchronous devices achieve high speed transfer rate s starting at 800 mb/sec/pin for general applications. the device is designed to comply with all ddr2 dram key features: 1. posted cas with additive latency, 2. write latency = read latency - 1, 3. normal and weak strengt h data-output driver, 4. off-chip driver (ocd) impedance adjustment 5. on-die termination (odt) function. all of the control and address inputs are synchronized with a pair of externally s upplied differential clocks. inputs are latch ed at the cross point of differential clocks (ck rising and ck falling). all i/os are synchronized with a single ended dqs or differential dqs-dqs pair in a source synchronous fashion. a 15-bit address bus is used to convey ro w, column and bank address information in a ras -cas multiplexing style. an auto-refresh and self-refresh mode is provi ded along with various power-saving power-down modes. the functionality described and the timing specifications included in this data sheet are for t he dll enabled mode of operation . the ddr2 sdram is available in p-tfbga package.
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 5 07222008-fvt6-k01b 2 configuration 2.1 chip configuration the chip configuration of a ddr2 sdram is listed by function in table 2 . the abbreviations used in the ball# and buffer type columns are explained in table 3 and table 4 respectively. the ball numbering for the fbga package is depicted in figure 1 . table 2 chip configuration of ddr2 sdram ball# name ball type buffer type function clock signals j8 ck i sstl clock signal ck, complementary clock signal ck note: ck and ck are differential syst em clock inputs. all address and control inputs are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossing of ck and ck (both direction of crossing) k8 ck i sstl k2 cke i sstl clock enable note: cke high activates and cke low deactivates internal clock signals and device input buffers and output drivers. taking c ke low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit and for self-refresh entry. input buffers excluding cke are disabled during self-refresh. cke is used asynchronously to detect self-refresh exit condition. self-refresh termination itself is synchronous. after v ref has become stable during power-on and initialisation sequence, it must be maintained for proper operation of the cke receiver. for proper self- refresh entry and exit, v ref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power-down control signals k7 ras i sstl row address strobe (ras), column address strobe (cas), write enable (we) l7 cas i sstl k3 we i sstl l8 cs i sstl chip select address signals l2 ba0 i sstl bank address bus 1:0 l3 ba1 i sstl
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 6 07222008-fvt6-k01b m8 a0 i sstl address signal 12:0, address signal 10/autoprecharge m3 a1 i sstl m7 a2 i sstl n2 a3 i sstl n8 a4 i sstl n3 a5 i sstl n7 a6 i sstl p2 a7 i sstl p8 a8 i sstl p3 a9 i sstl m2 a10 i sstl ap i sstl p7 a11 i sstl r2 a12 i sstl data signals g8 dq0 i/o sstl data signal 15:0 note: bi-directional data bus. dq[15:0] g2 dq1 i/o sstl h7 dq2 i/o sstl h3 dq3 i/o sstl h1 dq4 i/o sstl h9 dq5 i/o sstl f1 dq6 i/o sstl f9 dq7 i/o sstl c8 dq8 i/o sstl c2 dq9 i/o sstl d7 dq10 i/o sstl d3 dq11 i/o sstl d1 dq12 i/o sstl d9 dq13 i/o sstl b1 dq14 i/o sstl b9 dq15 i/o sstl data strobe b7 udqs i/o sstl data strobe upper byte note: udqs corresponds to the data on dq[15:8] a8 udqs i/o sstl f7 ldqs i/o sstl data strobe lower byte note: ldqs corresponds to the data on dq[7:0] e8 ldqs i/o sstl data mask b3 udm i sstl data mask upper/lower byte note: ldm and udm are the input mask signals and control the lower or upper bytes. f3 ldm i sstl power supplies ball# name ball type buffer type function
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 7 07222008-fvt6-k01b table 3 abbreviations for ball type table 4 abbreviations for buffer type a9,c1,c3,c7,c9 v ddq pwr ? i/o driver power supply a1 v dd pwr ? power supply a7,b2,b8,d2,d8 v ssq pwr ? i/o driver power supply a3,e3 v ss pwr ? power supply power supplies j2 v ref ai ? i/o reference voltage e9, g1, g3, g7, g9 v ddq pwr ? i/o driver power supply j1 v ddl pwr ? power supply e1, j9, m9, r1 v dd pwr ? power supply e7, f2, f8, h2, h8 v ssq pwr ? i/o driver power supply j7 v ssdl pwr ? power supply a3, e3,j3,n1,p9 v ss pwr ? power supply not connected a2, e2, r3, r7, r8, l1 nc nc ? not connected other balls k9 odt i sstl on-die termination control note: odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal. an emrs(1) control bit enables or disables the odt functionality. abbreviation description i standard input-only ball. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding ball has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. ball# name ball type buffer type function
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 8 07222008-fvt6-k01b figure 1 chip configuration, pg-tfbga-84 (top view) notes 1. udqs/udqs is data strobe for dq[15:8], ldqs/ldqs is data strobe for dq[7:0] 2. ldm is the data mask signal for dq[7:0], udm is the data mask signal for dq[15:8] 3. v ddl and v ssdl are power and ground for the dll. v ddl is connected to v dd on the device. v dd , v ddq , v ssdl , v ss and v ssq are isolated on the device. - 0 0 4 6 $ $ . # ! 6 3 3 1 .# 6 3 3 # + % # + 6 3 3 5 $ - $ 1 6 $ $ 1 $ 1 $ 1 6 3 3 6 $ $ , ! 6 3 3 1 $ 1 , $ 1 3 2 ! 3 6 $ $ ! " # $ & ' ( * % , - + . $ 1 6 $ $ " ! " ! ! ! 0 ! 6 3 3 6 $ $ 1 $ 1 $ 1 6 3 3 $ , ! ! ! $1 . # 6 $ $ . # 0 2 ! ! ! ! . # 6 3 3 $ 1 6 $ $ 1 6 3 3 1 $ 1 , $ - 6 $ $ 1 6 $ $ 1 $1 6 3 3 1 $1 6 2 % & 7 % . # ! ! 5$ 1 3 5 $ 1 3 $ 1 6 $ $ 1 6 $ $ 1 $ 1 6 3 3 1 $ 1 6 3 3 1 6 $ $ 1 , $ 1 3 6 3 3 1 6 $ $ 1 $ 1 6 $ $ 1 6 3 3 1 # + 6 $ $ / $ 4 # ! 3 # 3 6 3 3 1 6 3 3 1
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 9 07222008-fvt6-k01b 2.2 ddr2 addressing this chapter describes the ddr2 addressing. table 5 ddr2 addressing configuration 32 mb x16 1) 1) referred to as ?org? note bank address ba[1:0] number of banks 4 auto precharge a10 / ap row address a[12:0] column address a[9:0] number of column address bits 10 2) 2) referred to as ?colbits? number of i/os 16 page size [bytes] 2048 (2 k) 3) 3) pagesize = 2 colbits org/8 [bytes]
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 10 07222008-fvt6-k01b 3 functional description table 6 mode register definition (ba[1:0] = 00 b ) field bits type 1) description ba1 14 reg. addr. bank address [1] 0 b ba1 bank address ba0 13 bank address [0] 0 b ba0 bank address pd 12 w active power-down mode select 0 b pd fast exit 1 b pd slow exit wr [11:9] w write recovery 2) note: all other bit combinations are illegal. 001 b wr 2 010 b wr 3 011 b wr 4 100 b wr 5 101 b wr 6 110 b wr 7 dll 8 w dll reset 0 b dll no 1 b dll yes tm 7 w test mode 0 b tm normal mode 1 b tm vendor specific test mode cl [6:4] w cas latency note: all other bit combinations are illegal. 011 b cl 3 100 b cl 4 101 b cl 5 110 b cl 6 111 b cl 7 03%7 % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ 3 ' : 5 % / u h j d g g u z z z z z z ' / / 7 0 & / % 7 z
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 11 07222008-fvt6-k01b table 7 extended mode register definition (ba[1:0] = 01 b ) bt 3 w burst type 0 b bt sequential 1 b bt interleaved bl [2:0] w burst length note: all other bit combinations are illegal. 010 b bl 4 011 b bl 8 1) w = write only register bits 2) number of clock cycles for write re covery during auto-precharge. wr in cl ock cycles is calc ulated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next integer: wr [cycles] t wr (ns) / t ck (ns). the mode register must be progra mmed to fulfill the minimum requirement for the analogue t wr timing wr min is determined by t ck.max and wr max is determined by t ck.min . field bits type 1) description ba1 14 reg. addr. bank address [1] 0 b ba1 bank address ba0 13 bank address [0] 1 b ba0 bank address qoff 12 w output disable 0 b qoff output buffers enabled 1 b qoff output buffers disabled a11 11 w address bus [11] 0 b a11 address bit 11 dqs 10 w complement data strobe (dqs output) 0 b dqs enable 1 b dqs disable ocd program [9:7] w off-chip driver ca libration program 000 b ocd ocd calibration mode exit, maintain setting 001 b ocd drive (1) 010 b ocd drive (0) 100 b ocd adjust mode 111 b ocd ocd calibration default field bits type 1) description 03%7 % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ 4 r i i ' 4 6 2 & ' 3 u r j u d p 5 w w $ / 5 w w ' , & ' / / u h j d g g u z z z z z z z
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 12 07222008-fvt6-k01b a0 is used for dll enable or disable. a1 is used for enabling half-strength data-output driver. a2 and a6 enables on-die termination (odt) and sets the r tt value. a[5:3] are used for additive latency settings and a[9:7] enables the ocd impedance adjustment mode. a10 enables or disables the differential dqs. address bit a12 have to be set to 0 for normal operation. with a12 set to 1 the sdram outputs are disabled and in hi-z. 1 on ba0 and 0 for ba1 have to be set to access the emrs(1). table 8 emrs(2) programming extended mode register definition (ba[1:0]=10 b ) al [5:3] w additive latency note: all other bit combinations are illegal. 000 b al 0 001 b al 1 010 b al 2 011 b al 3 100 b al 4 101 b al 5 110 b al 6 r tt 6,2 w nominal termination resistance of odt note: see table 18 ?odt dc electrical ch aracteristics? on page 18 00 b rtt (odt disabled) 01 b rtt 75 ohm 10 b rtt 150 ohm 11 b rtt 50 ohm dic 1 w off-chip driver im pedance control 0 b dic full (driver size = 100%) 1 b dic reduced dll 0 w dll enable 0 b dll enable 1 b dll disable 1) w = write only register bits field bits type 1) description field bits type 1) description ba1 14 reg. addr., bank address [1] 1 b ba1 bank address ba0 13 bank address [0] 0 b ba0 bank address a [12:8] w address bus 00000 b a address bits 03%7 %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ uhjdggu 65) 3$65
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 13 07222008-fvt6-k01b table 9 emr(3) programming extended mode register definition( ba[1:0]=11 b ) srf 7 w address bus, high temperature self refresh rate for t case > 85 c 0 b a7 disable 1 b a7 enable 2) a [6:3] w address bus 0000 b a address bits partial self refresh for 4 banks pasr [2:0] w address bus, partial array self refresh for 4 banks 3) 000 b pasr0 full array 001 b pasr1 half array (ba[1:0]=00, 01) 010 b pasr2 quarter array (ba[1:0]=00) 011 b pasr3 not defined 100 b pasr4 3/4 array (ba[1:0]=01, 10, 11) 101 b pasr5 half array (ba[1:0]=10, 11) 110 b pasr6 quarter array (ba[1:0]=11) 111 b pasr7 not defined 1) w = write only 2) when dram is operated at 85 c t case 95 c the extended self refresh rate must be enabled by setting bit a7 to "1" before the self refresh mode can be entered. 3) if pasr (partial array self refresh) is enabled, data located in areas of the array beyond the specified location will be los t if self refresh is entered. data integrity will be maintained if t ref conditions are met and no self refresh command is issued field bits type 1) 1) w = write only description ba1 14 reg.addr bank adress 1 b ba1 bank address ba0 13 bank adress 1 b ba0 bank address a [12:0] w address bus 0000000000000 b address bits field bits type 1) description 03%7 % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ u h j d g g u
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 14 07222008-fvt6-k01b table 10 odt truth table note: x = don?t care; 0 = bit set to low; 1 = bit set to high table 11 burst length and sequence notes 1. page size and length is a function of i/o organization: page size = 2 kbyte; page length = 1024 2. order of burst access for sequential addressing is ?nibble- based? and therefore diff erent from sdr or ddr components input pin emrs(1) address bit a10 emrs(1) address bit a11 dq[7:0] x dq[15:8] x ldqs x ldqs 0x udqs x udqs 0x ldm x udm x burst length star ting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 0 0 0, 1, 2, 3 0, 1, 2, 3 0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 15 07222008-fvt6-k01b 4 truth tables table 12 command truth table function cke cs ras cas we ba0 ba1 a[12:11] a10 a[9:0] note 1)2)3) 1) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 2) ?x? means ?h or l (but a defined logic level)?. 3) operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initializa tion sequence before normal operation can continue. previous cycle current cycle (extended) mode register set h h l l l l ba op code 4)5) 4) all ddr2 sdram commands are defined by states of cs , we , ras , cas , and cke at the rising edge of the clock. 5) bank addresses ba[1:0] determine which bank is to be operated upon. for (e)mrs ba[1:0] selects an (extended) mode register. auto-refresh h h l l l h x x x x 4) self-refresh entry h l l l l h x x x x 4)6) 6) v ref must be maintained during self refresh operation. self-refresh exit l h h x x x x x x x 4)6)7) 7) self refresh exit is asynchronous. lh h h single bank precharge h h l l h l ba x l x 4)5) precharge all banks h h l l h l x x h x 4) bank activate h h l l h h ba row address 4)5) write h h l h l l ba column l column 4)5)8) 8) burst reads or writes at bl = 4 cannot be terminated. write with auto-precharge h h l h l l ba column h column 4)5)8) read h h l h l h ba column l column 4)5)8) read with auto-precharge h h l h l h ba column h column 4)5)8) no operation h x l h h h x x x x 4) device deselect h x h x x x x x x x 4) power down entry h l h x x x x x x x 4)9) 9) the power down mode does not perform any refresh operations. lh h h power down exit l h h x x x x x x x 4)9) lh h h
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 16 07222008-fvt6-k01b table 13 clock enable (cke) truth table for synchronous transitions table 14 data mask (dm) truth table current state 1) 1) current state is the state of the ddr2 sdram immediately prior to clock edge n. cke command (n) 2)3) ras, cas, we, cs 2) command (n) is the command registered at clock e dge n, and action (n) is a result of command (n) 3) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. action (n) 2) note 4)5) 4) cke must be maintained high while the device is in ocd calibration mode. 5) operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initializa tion sequence before normal operation can continue. previous cycle 6) (n-1) 6) cke (n) is the logic state of cke at clock edge n; c ke (n-1) was the state of cke at the previous clock edge. current cycle 6) (n) power-down l l x maintain power-down 7)8)11) 7) the power-down mode does not perform any refresh operations. the duration of power-down mode is therefor limited by the refre sh requirements 8) ?x? means ?don?t care (including floating around v ref )? in self refresh and power down. however odt must be driven high or low in power down if the odt function is enabled (bit a2 or a6 set to ?1? in emrs(1)). l h deselect or nop power-down exit 7)9)10)11) 9) all states and sequences not shown ar e illegal or reserved unless explicitly described else where in this document. 10) valid commands for power-down entry and exit are nop and deselect only. 11) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 clocks of registration. thus, after any cke trans ition, cke may not transition from its v alid level during the time period of t is + 2 t cke + t ih . self refresh l l x maintain self refresh 8)11)12) 12) v ref must be maintained during self refresh operation. l h deselect or nop self refresh exit 9)12)13)14) 13) on self refresh exit deselect or nop commands must be issued on every clock edge occurring during the txsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 14) valid commands for self refresh exit are nop and deselct only. bank(s)active h l deselect or nop active power-down entry 7)9)10)11)15) 15) power-down and self refresh can not be entered while read or write operations, (extended) mode register operations, precharg e or refresh operations are in progress. all banks idle h l deselect or no p precharge power-down entry 9)10)11)15) h l autorefresh self refresh entry 7)11)14)16) 16) self refresh mode can only be entered from the all banks idle state. any state other than listed above h h refer to the command truth table 17) 17) must be a legal command as defined in the command truth table. name (function) dm dqs note write enable l valid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit h x 1)
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 17 07222008-fvt6-k01b 5 electrical characteristics this chapter describes the electrical characteristics. 5.1 absolute maximum ratings caution is needed not to exceed absolute maximum ratings of the dram device listed in table 18 at any time. table 15 absolute maximum ratings attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. table 16 dram component operating temperature range symbol parameter rating unit note min. max. v dd voltage on v dd pin relative to v ss ?1.0 +2.3 v 1) 1) when v dd and v ddq and v ddl are less than 500 mv; v ref may be equal to or less than 300 mv. v ddq voltage on v ddq pin relative to v ss ?0.5 +2.3 v 1)2) v ddl voltage on v ddl pin relative to v ss ?0.5 +2.3 v 1)2) v in , v out voltage on any pin relative to v ss ?0.5 +2.3 v 1) t j junction temperature ? +125 c 1) t stg storage temperature ?55 +150 c 1)2) 2) storage temperature is the case surface temperature on the center/top side of the dram. symbol parameter rating unit note min. max. t case operating temperature 0 95 c 1)2)3)4) 1) operating temperature is the case surface te mperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where al l dram specification will be supported. during operation, the dr am case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) above 85 c the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c t case temperature range, the high temperature self refresh has to be enabled by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50%
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 18 07222008-fvt6-k01b 5.2 dc characteristics table 17 recommended dc operating conditions (sstl_18) table 18 odt dc electrical characteristics table 19 input and output leakage currents symbol parameter rating unit notes min. typ. max. v dd supply voltage 1.7 1.8 1.9 v 1)2) 1) hyb18t512161cf?[16/20] 2) v ddq tracks with v dd , v dddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together. v dddl supply voltage for dll 1.7 1.8 1.9 v 1)2) v ddq supply voltage for output 1.7 1.8 1.9 v 1)2) v ref input reference voltage 0.49 v ddq 0.5 v ddq 0.51 v ddq v 3)4) 3) the value of v ref may be selected by the user to provide optimum noi se margin in the system. typically the value of v ref is expected to be about 0.5 v ddq of the transmitting device and v ref is expected to track variations in v ddq . 4) peak to peak ac noise on v ref may not exceed 2% v ref (dc) v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v 5) 5) v tt is not applied directly to the device. v tt is a system supply for signal terminati on resistors, is expected to be set equal to v ref , and must track variations in die dc level of v ref . parameter / condition sym bol min. nom. max. unit note termination resistor impedance value for emrs(1)[a6,a2] = [0,1]; 75 ohm rtt1(eff) 60 75 90 1) 1) measurement definition for rtt(eff): apply v ih(ac) and v il(ac) to test pin separately, then measure current i(v ihac ) and i(v ilac ) respectively. rtt(eff) = (v ih(ac) ? v il(ac) ) /(i(v ihac ) ? i(v ilac )). termination resistor impedance value for emrs(1)[a6,a2] =[1,0]; 150 ohm rtt2(eff) 120 150 180 1) termination resistor impedance value for emrs(1)(a6,a2)=[1,1]; 50 ohm rtt3(eff) 40 50 60 1) deviation of v m with respect to v ddq / 2 delta v m ?6.00 ? + 6.00 % 2) 2) measurement definition for v m : turn odt on and measure voltage (v m ) at test pin (midpoint) with no load: delta v m = ((2 x v m /v ddq )? 1) x 100% symbol parameter / condi tion min. max. unit notes iil input leakage current; any input 0 v < v in < v dd ?2 +2 a 1) 1) all other pins not under test = 0 v iol output leakage current; 0 v < vout < v ddq ?5 +5 a 2) 2) dq?s, ldqs, ldqs , udqs, udqs , dqs, dqs are disabled and odt is turned off
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 19 07222008-fvt6-k01b 5.3 dc & ac characteristics ddr2 sdram pin timing are specified for either single ended or differential mode depending on the setting of the emrs(1) ?enable dqs ? mode bit; timing advantages of differential mode are realized in system des ign. the method by which the ddr2 sdram pin timing are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these ti ming relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is verified by design and characterization but not subject to production test. in single ended mode, the dqs signals are internally disabled and don?t care. table 20 dc & ac logic input levels table 21 single-ended ac input test conditions symbol parameter min. max. units v ih(dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il(dc) dc input low ?0.3 v ref ? 0.125 v v ih(ac) ac input logic high v ref + 0.250 ? v v il(ac) ac input low ? v ref ? 0.250 v symbol condition value unit notes v ref input reference voltage 0.5 x v ddq v 1) 1) input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. v swing.max input signal maximum peak to peak swing 1.0 v 1) slew input signal minimum slew rate 1.0 v / ns 2)3) 2) the input signal minimum slew rate is to be maintained over the range from v ih(ac).min to v ref for rising edges and the range from v ref to v il(ac).max for falling edges as shown in figure 2 3) ac timings are referenced with input waveforms switching from v il(ac) to v ih(ac) on the positive transitions and v ih(ac) to v il(ac) on the negative transitions.
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 20 07222008-fvt6-k01b figure 2 single-ended ac input test conditions diagram table 22 differential dc and ac in put and output logic levels figure 3 differential dc and ac input and output logic levels diagram symbol parameter min. max. unit notes v in(dc) dc input signal voltage ?0.3 v ddq + 0.3 ? 1) 1) v in(dc) specifies the allowable dc execution of eac h input of differential pair such as ck, ck , dqs, dqs etc. v id(dc) dc differential input voltage 0.25 v ddq + 0.6 ? 2) 2) v id(dc) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(dc) ? v il(dc) . v id(ac) ac differential input voltage 0.5 v ddq + 0.6 v 3) 3) v id(ac) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(ac) ? v il(ac) . v ix(ac) ac differential cross point input voltage 0.5 v ddq ? 0.175 0.5 v ddq + 0.175 v 4) 4) the value of v ix(ac) is expected to equal 0.5 v ddq of the transmitting device and v ix(ac) is expected to track variations in v ddq . v ix(ac) indicates the voltage at which differential input signals must cross. v ox(ac) ac differential cross point output voltage 0.5 v ddq ? 0.125 0.5 v ddq + 0.125 v 5) 5) the value of v ox(ac) is expected to equal 0.5 v ddq of the transmitting device and v ox(ac) is expected to track variations in v ddq . v ox(ac) indicates the voltage at which differential input signals must cross. 'howd75 'howd7) 9 6:,1*0$; 9 ,+df plq 9 ,+gf plq 9 5() 9 ,/gf pd[ 9 ,/df pd[ 9 66 5l l 6o 9 ,+df plq9 5() 9 5() 9 ,/df pd[ ) ool 6o # r o s s i n g 0 o i n t 6 $ $ 1 6 3 3 1 6 ) $ 6 ) 8 o r 6 / 8 6 4 2 6 # 0
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 21 07222008-fvt6-k01b 5.4 output buffer characteristics table 23 full strength calibrated pull-up driver characteristics table 24 full strength calibrated pull -down driver characteristics voltage (v) calibrated pull -up driver current [ma] nominal minimum 1) (21 ohms) 1) the driver characteristics evaluation conditions are nominal minimum 95 c ( t case ). v ddq = 1.7 v, any process nominal low 2) (18.75 ohms) 2) the driver characteristics ev aluation conditions are nominal low and nominal high 25 c ( t case ), v ddq = 1.8 v, any process nominal (18 ohms) 3) 3) the driver characteristics evaluat ion conditions are nominal 25 c ( t case ), v ddq = 1.8 v, typical process nominal high 2) (17.25 ohms) nominal maximum 4) (15 ohms) 4) the driver characteristics evaluation conditions are nominal maximum 0 c ( t case ), v ddq = 1.9 v, any process 0.2 ?9.5 ?10.7 ?11.4 ?11.8 ?13.3 0.3 ?14.3 ?16.0 ?16.5 ?17.4 ?20.0 0.4 ?18.3 ?21.0 ?21.2 ?23.0 ?27.0 voltage (v) calibrated pull -down driver current [ma] nominal minimum 1) (21 ohms) 1) the driver characteristics evaluation conditions are nominal minimum 95 c ( t case ). v ddq = 1.7 v, any process nominal low 2) (18.75 ohms) 2) the driver characteristics ev aluation conditions are nominal low and nominal high 25 c ( t case ), v ddq = 1.8 v any process nominal 3) (18 ohms) 3) the driver characteristics evaluat ion conditions are nominal 25 c ( t case ), v ddq = 1.8 v, typical process nominal high 2) (17.25 ohms) nominal maximum 4) (15 ohms) 4) the driver characteristics evaluation conditions are nominal maximum 0 c ( t case ), v ddq = 1.9 v, any process 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 22 07222008-fvt6-k01b 5.5 input / output capacitance table 25 input / output capacitance symbol parameter min. max. unit cck input capacitance, ck and ck 1.0 2.0 pf cdck input capacitance delta, ck and ck ?0.25 pf ci input capacitance, all other input-only pins 1.0 1.75 pf cdi input capacitance delta, all other input-only pins ? 0.25 pf cio input/output capacitance, dq, dm, dqs, dqs 2.5 3.5 pf cdio input/output capacitance delta, dq, dm, dqs, dqs ?0.5 pf
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 23 07222008-fvt6-k01b 5.6 overshoot and undershoot specification table 26 ac overshoot / undershoot specification for address and control pins figure 4 ac overshoot / undershoot diagram for address and control pins parameter ?16 ?20 unit maximum peak amplitude allowed for overshoot area 0.5 0.5 v maximum peak amplitude allowed for undershoot area 0.5 0.5 v maximum overshoot area above v dd 0.80 0.80 v.ns maximum undershoot area below v ss 0.80 0.80 v.ns 03(7 9rowv9 9 '' 9 66 0d[lpxp$psolwxgh 7lphqv 0d[lpxp$psolwxgh 2yhuvkrrw$uhd 8qghuvkrrw$uhd
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 24 07222008-fvt6-k01b table 27 ac overshoot / undershoot specification for clock, data, strobe and mask pins figure 5 ac overshoot / undershoot diagram for clock, data, strobe and mask pins parameter ?16 ?20 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 v maximum overshoot area above v ddq 0.23 0.23 v.ns maximum undershoot area below v ssq 0.23 0.23 v.ns 03(7 9rowv9 9 ''4 9 664 0d[lpxp$psolwxgh 7lphqv 0d[lpxp$psolwxgh 2yhuvkrrw$uhd 8qghuvkrrw$uhd
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 25 07222008-fvt6-k01b 5.7 ac characteristics 5.7.1 speed grade definitions table 28 speed grade definition speed grade symbol ?16 ?20 unit note parameter min. max. min. max. clock frequency @ cl = 3 t ck 58 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) under the ?reference load for timing measurements?. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , input reference level is the crosspoint when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 38 38 ns 1)2)3)4) @ cl = 6 t ck 2.5 8 2.5 8 ns 1)2)3)4) @ cl = 7 t ck 1.66 8 2.0 8 ns 1)2)3)4) row active time t ras 45 70k 45 70k ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? 15 ? ns 1)2)3)4) row precharge time t rp 15 ? 15 ? ns 1)2)3)4)
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 26 07222008-fvt6-k01b 5.7.2 ac timing parameters list of timing parameters table 29 timing parameter by speed grade parameter symbol ?16 ?20 unit notes 1) 2)3)4)5)6) min. max. min. max. dq output access time from ck / ck t ac ?400 +400 ?450 +450 ps cas a to cas b command period t ccd 2?2? t ck ck, ck high-level width t ch 0.45 0.55 0.45 0.55 t ck cke minimum high and low pulse width t cke 3?3? t ck ck, ck low-level width t cl 0.45 0.55 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ?wr+ t rp ? t ck 7)18) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? t is + t ck + t ih ?? ns 8) dq and dm input hold time (differential data strobe) t dh 90 ?? 145 ?? ps 9) dq and dm input hold time (single ended data strobe) t dh1 -160 ?? -105 ?? ps 9) dq and dm input pulse width (each input) t dipw 0.35 ? 0.35 ? t ck dqs output access time from ck / ck t dqsck ?400 +400 ?450 + 450 ps 9) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 280 ? 280 ps 10) write command to 1st dqs latching transition t dqss wl ? 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 t ck dq and dm input setup time (differential data strobe) t ds -35 20 ps 9) dq and dm input setup time (single ended data strobe) t ds1 ?160 ?105 ps 9) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck dqs falling edge to ck se tup time (write cycle) t dss 0.2 ? 0.2 ? t ck clock half period t hp min. ( t cl, t ch ) min. ( t cl, t ch ) 11) data-out high-impedance time from ck / ck t hz ? t ac.max ? t ac.max ps 12) address and control input hold time t ih 475 ? 525 ? ps address and control input pulse width (each input) t ipw 0.6 ? 0.6 ? t ck address and control input setup time t is 350 ? 400 ? ps dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max 2 t ac.min t ac.max ps 12) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max t ac.min t ac.max ps 12) mode register set command cycle time t mrd 2?2? t ck ocd drive mode output delay t oit 0 12 0 12 ns data output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ?
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 27 07222008-fvt6-k01b data hold skew factor t qhs ? 380 ? 380 ps average periodic refresh interval t refi ? 7.8 ? 7.8 s 13)14) ? 3.9 ? 3.9 s 13)15) auto-refresh to active/auto-refresh command period t rfc 105 ? 105 ? ns 16) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 12) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 12) active bank a to active bank b command period t rrd 10 ? 10 ? ns 14)17) internal read to precharge command delay t rtp 7.5 ? 7.5 ? ns write preamble t wpre 0.35 x t ck ? 0.35 x t ck ? t ck write postamble t wpst 0.40 0.60 0.40 0.60 t ck 17) write recovery time for write without auto- precharge t wr 11.6 ? 14 ? ns write recovery time for write with auto-precharge wr t wr / t ck t wr / t ck t ck 18) internal write to read command delay t wtr 7.5 ? 7.5 ? ns 19) exit power down to any valid command (other than nop or deselect) t xard 2?2? t ck 20) exit active power-down mode to read command (slow exit, lower power) t xards 10 ? al ? 10 ? al ? t ck 20) exit precharge power-down to any valid command (other than nop or deselect) t xp 2?2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? 200 ? t ck 1) v ddq , v dd refer to chapter 1 . 2) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 5 of this data sheet. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross.the dqs / dqs , input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/ck , dqs / dqs is defined in chapter 5.3 of this data sheet. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . see chapter 5 for the reference load for timing measurements. 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 8) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. in case of clock frequency ch ange during power-down, a specif ic procedure is required. 9) timing is referenced to industrial standard definition 10) consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 11) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the act ual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 12) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. parameter symbol ?16 ?20 unit notes 1) 2)3)4)5)6) min. max. min. max.
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 28 07222008-fvt6-k01b 5.7.3 odt ac electrical characteristics table 30 odt ac characteristics and operating conditions for all bins 13) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 14) 0 c t case 85 c 15) 85 c < t case 95 c 16) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 17) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 18) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 19) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 20) user can choose two different active pow er-down modes for additional power saving via mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 n ck 1) 1) unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ? n ck ? represents one clock cycl e of the input clock, counting the actual clock edges. example: t xp = 2 [ n ck ] means; if power down exit is registered at t m , an active command may be registered at t m + 2, even if ( t m + 2 - t m ) is 2 x t ck.avg + t err.2per(min) . t aon odt turn-on t ac.min t ac.max +0.7ns ns 1)2) 2) odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is w hen the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. t aond is 2 clock cycles after the clock edge that registered a first odt hi gh counting the actual input clock edges. t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max +1 ns ns 1) t aofd odt turn-off delay 2.5 2.5 n ck 1) t aof odt turn-off t ac.min t ac.max +0.6ns ns 1)3) 3) odt turn off time min is when the device starts to turn off od t resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd , which is interpreted differently per speed bin. if t ck(avg) = 3 ns is assumed, t aofd is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first odt low and by counting the actual input cl ock edges. t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max +1ns ns 1) t anpd odt to power down mode entry latency 3 ? n ck 1) t axpd odt power down exit latency 8 ? n ck 1)
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 29 07222008-fvt6-k01b 6 currents measurement conditions table 31 i dd measurement conditions parameter symbol note operating current - one bank active - precharge t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , cke is high, cs is high between valid commands. address and control inputs are switch ing; databus inputs are switching. i dd0 1)2)3)4)5)6)7) operating current - one bank active - read - precharge i out = 0 ma, bl = 4, t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , t rcd = t rcd(idd) , al = 0, cl = cl(idd); cke is high, cs is high between valid commands. address and control inputs are switching; databus inputs are switching. i dd1 1)2)3)4)5)6)7) precharge power-down current all banks idle; cke is low; t ck = t ck(idd) ;other control and address input s are stable; data bus inputs are floating . i dd2p 1)2)3)4)5)6)7) precharge standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are switching, data bus inputs are switching . i dd2n 1)2)3)4)5)6)7) precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are stable, data bus inputs are floating. i dd2q 1)2)3)4)5)6)7) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable; data bus inputs are floating. mrs a12 bit is set to ?0? (fast power-down exit). i dd3p(0) 1)2)3)4)5)6)7) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and a ddress inputs are stable, data bus inputs are floating. mrs a12 bit is set to 1 (slow power-down exit); i dd3p(1) 1)2)3)4)5)6)7) active standby current all banks open; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd3n 1)2)3)4)5)6)7) operating current burst read: all banks open; continuous bu rst reads; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max.(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r 1)2)3)4)5)6)7) operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w 1)2)3)4)5)6)7) burst refresh current t ck = t ck(idd) , refresh command every t rfc = t rfc(idd) interval, cke is high, cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5b 1)2)3)4)5)6)7) distributed refresh current t ck = t ck(idd) , refresh command every t refi = 7.8 s interval, cke is low and cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5d 1)2)3)4)5)6)7)
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 30 07222008-fvt6-k01b 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v; 2) hyb18t512161cf?16/20 3) i dd specifications are tested after the device is properly initialized 4) i dd parameter are specified with odt disabled 5) data bus consists of dq, dm, dqs, dqs , ldqs, ldqs , udqs and udqs 6) definitions for i dd : see table 32 7) timing parameter minimum and maximum values for i dd current measurements 8) a = activate, ra = read with auto-precharge, d=deselect table 32 definition for i dd self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and a ddress inputs are floating, data bus inputs are floating. i dd6 1)2)3)4)5)6)7) operating bank interleave read current all banks interleaving reads, i out = 0 ma; bl = 4, cl = cl (idd) , al = t rcd(idd) -1 t ck(idd) ; t ck = t ck(idd) , t rc = t rc(idd) , t rrd = t rrd(idd) ; cke is high, cs is high between valid commands. address bus inputs are stable during deselects; data bus is switching. i dd7 1)2)3)4)5)6)7)8) parameter description low defined as v in v il(ac).max high defined as v in v ih(ac).min stable defined as inputs are stable at a high or low level floating defined as inputs are v ref = v ddq / 2 switching defined as: inputs are changing between high a nd low every other clock (once per two clocks) for address and control signals, and inputs changing between hi gh and low every other clock (once per clock) for dq signals not including mask or strobes parameter symbol note
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 31 07222008-fvt6-k01b table 33 i dd specification 6.1 i dd test conditions for testing the i dd parameters, the following timing parameters are used: table 34 i dd measurement test condition speed grade ?16 ?20 unit note symbol typ typ. i dd0 93 84 ma i dd1 101 92 ma i dd2p 66ma i dd2n 60 53 ma i dd2q 58 51 ma i dd3p(0) 27 23 ma 1) 1) mrs(12)=0 i dd3p(1) 88ma 2) 2) mrs(12)=1 i dd3n 67 60 ma i dd4r 221 189 ma i dd4w 206 177 ma i dd5b 122 115 ma i dd5d 77ma 3) 3) 0c t case 85c i dd6 44ma 3) i dd7 197 190 ma parameter symbol ?16 ?20 unit notes cas latency cl idd 77t ck clock cycle time t ckidd 1.66 2.0 ns active to read or write delay t rcd.idd 15 15 ns active to active / auto-refresh command period t rc.idd 60 60 ns active bank a to active bank b command delay t rrd.idd 10 10 ns 1) 1) 2 kb page size active to precharge command t ras.min.idd 45 45 ns t ras.max.idd 70k 70k ns precharge command period t rp.idd 15 15 ns auto-refresh to active / auto-refresh command period t rfc.idd 105 105 ns average periodic refresh interval 0 c t case 85 c t refi 7.8 7.8 s 85 c t case 95 c3.93.9 s
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 32 07222008-fvt6-k01b 6.1.1 on die termination (odt) current the odt function adds additional current consumption to t he ddr2 sdram when enabled by the emrs(1). depending on address bits a6 & a2 in the emrs(1) a ?weak? or ?strong? te rmination can be selected. the current consumption for any terminated input pin depends on whether the input pin is in tri-st ate or driving ?0? or ?1?, as long a odt is enabled during a given period of time. see table 35 table 35 odt current per terminated input pin note: for power consumption ca lculations the odt duty cycle has to be taken into account odt current emrs(1) state min. typ. max. unit enabled odt current per dq added i ddq current for odt enabled;odt is high; data bus inputs are floating i odto a6 = 0, a2 = 1 5 6 7.5 ma/dq a6 = 1, a2 = 0 2.5 3 3.75 ma/dq a6 = 1, a2 = 1 7.5 9 11.25 ma/dq active odt current per dq added i ddq current for odt enabled;odt is high; worst case of data bus inputs are stable or switching. i odtt a6 = 0, a2 = 1 10 12 15 ma/dq a6 = 1, a2 = 0 5 6 7.5 ma/dq a6 = 1, a2 = 1 15 18 22.5 ma/dq
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 33 07222008-fvt6-k01b 7 package 7.1 package dimension figure 6 package outline p(g)-tfbga-84 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 " -!8 -iddle of packages edges "ad unit marking "5- 0ackage orientation mark ! ? -). ? ? ? $ummy pads without ball ! x - - # # ! # x -!8 &0/?0' 4&"'!?? 3%!4).' 0,!.% # # x " -!8 -!8
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 34 07222008-fvt6-k01b 7.2 package thermal characteristics table 36 package thermal characteristics jesd51 theta_ja 1) 1) junction to ambient thermal resistance. the value has been obt ained by simulation using the c onditions stated in the industri al standard. theta_jc 2) 2) junction to case thermal resistance. the value has been obtained by simulation. jedec board 1s0p 2s0p air flow 0 m/s 1 m/s 3 m/s 0 m/s 1 m/s 3 m/s rth[k/w] 69 53 47 41 35 33 5
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 35 07222008-fvt6-k01b list of illustrations figure 1 chip configuration, pg-tfbga-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2 single-ended ac input test conditions diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 3 differential dc and ac input and output logic levels diagr am . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4 ac overshoot / undershoot diagram for address and control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5 ac overshoot / undershoot diagram for clock, data, strobe and mask pins . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6 package outline p(g)-tfbga-84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 36 07222008-fvt6-k01b list of tables table 1 ordering information for rohs compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 2 chip configuration of ddr2 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3 abbreviations for ball type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5 ddr2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6 mode register definition (ba[1:0] = 00 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7 extended mode register definition (ba[1:0] = 01 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8 emrs(2) programming extended mode register definition (ba[1:0]=10 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9 emr(3) programming extended m ode register definition( ba[1:0]=11 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 10 odt truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 11 burst length and sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 12 command truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 13 clock enable (cke) truth table for synchronous transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 14 data mask (dm) truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 15 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 16 dram component operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 17 recommended dc operating conditions (sstl_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 18 odt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 19 input and output leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 20 dc & ac logic input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 21 single-ended ac input test condition s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 22 differential dc and ac input and output logic levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 23 full strength calibrated pull-up driv er characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 24 full strength calibrated pull-down driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 25 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 26 ac overshoot / undershoot specification for address and co ntrol pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 27 ac overshoot / undershoot specification for clock, data, strobe and mask pins . . . . . . . . . . . . . . . . . . . . . 24 table 28 speed grade definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 29 timing parameter by speed grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 30 odt ac characteristics and operating conditions for all bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 31 i dd measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 32 definition for i dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 33 i dd specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 34 i dd measurement test condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 35 odt current per terminated input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 36 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
hyb18t512161cf 512-mbit double-data-rate-two sdram internet data sheet rev. 1.11, 2008-08 37 07222008-fvt6-k01b contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 chip configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 ddr2 addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4truthtables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 dc & ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 output buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5 input / output capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.6 overshoot and undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.7 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.7.1 speed grade definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.7.2 ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.7.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 currents measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 i dd test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1.1 on die termination (odt) current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2 package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
edition 2008-08 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2008. all rights reserved. legal disclaimer the information given in this internet data sh eet shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein an d/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any ki nd, including without limitation warranties of non-infringement of in tellectual property righ ts of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. under no circumstances may the qimonda product as referred to in this internet data sheet be used in 1. any applications that are intended for military usage (including but not limited to weaponry), or 2. any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices an d systems collectively referred to as "critical systems"), if a) a failure of the qimonda product can reasonable be expected to - directly or indirectly - (i) have a detrimental effect on such critical systems in terms of reliability, effectiveness or safety; or (ii) cause the failure of such critical systems; or b) a failure or malfunction of such critical systems ca n reasonably be expected to - directly or indirectly - (i) endanger the health or the life of the user of such critical systems or any other person; or (ii) otherwise cause material damages (including but not lim ited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com internet data sheet

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